The present invention is directed to a capacitor for a semiconductor device and a method for forming a capacitor for a semiconductor device. More particularly, the present invention is directed to a capacitor for a semiconductor device having a nodular shaped electrode and a method for forming such an electrode.
Advancements in semiconductor manufacture have led to increases in the density and miniaturization of microelectronic circuits. As an example, the manufacture of 1 Gb DRAMs is now possible and 4 Gb prototypes are currently being developed. A key requirement for achieving such high device packing density is the formation of suitable storage capacitors.
With increased packing density of memory cells, however, the area available for storage capacitors (i.e. storage nodes) has decreased. This has necessitated the development of storage capacitors having an increased capacitance. In general, storage capacitors can be formed as stacked structures or as trench structures. The present invention is directed in part to stacked structures and in another part to a combination stacked-trench structure.
Typically, a thin film stacked storage capacitor includes a lower electrode, an upper electrode, and a dielectric layer which is sandwiched between the electrodes. This capacitor structure is stacked on an insulating layer of a substrate. The insulating layer is typically formed from materials such as SiO2 and Si3N4 that are compatible with a silicon process. The lower electrode of the capacitor is connected to a field effect transistor (FET) formed on the substrate. A polycrystalline silicon layer has been used as the lower electrode of a capacitor. Such a polysilicon layer is sometimes referred to as a polysilicon or silicon electrode.
One way to increase the capacity of this type of capacitor is to use a dielectric layer formed with a high dielectric constant material. These high dielectric constant materials include inorganic non-metallic oxides in the paraelectric or ferro electric phase such as BaSrTiO3 (BST), BaTiO3, SrTiO3, PbZrO3 and others. Such high dielectric constant materials have a dielectric constant greater than 100. This is an order of magnitude larger than traditional dielectric materials, such as SiO2 and Si3N4, which have dielectric constants less than 10.
A problem with high capacitance capacitors is that generally high dielectric constant films cannot be formed directly over a polysilicon electrode. This is because an interface layer of silicon dioxide forms between the dielectric film and the polysilicon electrode. Such an interface layer reduces the effective dielectric constant of the dielectric material and defeats its purpose. For this reason, the lower electrode structure is typically formed as a stack comprising a barrier layer formed on the polysilicon electrode and a lower electrode formed on the barrier layer.
The barrier layer is typically formed from a conductive material, such as tantalum (Ta), titanium nitride (TiN), or tungsten nitride (WN). Such a barrier layer, in addition to preventing oxidation of the polysilicon electrode, also functions to prevent silicon diffusion into the lower electrode. Such silicon diffusion increases the resistivity of the lower electrode and could lead to the formation of a thin layer of SiO2 layer on top of the lower electrode.
Another problem associated with the use of high dielectric constant films is that these films must be deposited at relatively high temperatures (e.g. 600xc2x0 C. to 700xc2x0 C.). Because of the high process temperatures that are required, the lower electrode of such a capacitor is typically formed of a high melting point, non-oxidizing metal such as platinum, palladium or rhodium or of a conducting oxide such as ruthenium oxide, iridium oxide, osmium oxide or rhodium oxide. A non-oxidizing material is required for the lower electrode because a traditional electrode material such as aluminum, titanium, nichrome or copper will oxidize at the high temperatures, increasing the resistivity of the electrode.
A prior art stacked capacitor 10 employing a high dielectric constant dielectric film 26 is shown in FIG. 1. In FIG. 1, a semiconductor substrate 12 includes a FET (not shown) formed with a pair of insulated gate electrodes 14 and 16. An insulating layer 18 is formed over the FET and gate electrodes 14 and 16. The capacitor 10 is stacked on the insulating layer 18. A polysilicon plug 20 is formed in a contact hole formed through the insulating layer 18 to the source or drain region 30 of the FET.
The capacitor 10 includes a lower electrode 22 having a rectangular cross section, an upper electrode 24 and a dielectric film 26 formed between the lower electrode 22 and the upper electrode 24. The capacitor 10 also includes a barrier layer 28 formed between the lower electrode 22 and the polysilicon plug 20.
Such a capacitor is subject to several limitations. First, the dielectric layer 26 must be formed over the stepped surface contour provided by the stack formed by the lower electrode 22 and the barrier layer 28. Poor step coverage of the dielectric material 28 over the lower electrode 22 promotes charge leakage at the corners of the dielectric material 26 in the completed capacitor structure. To prevent this leakage, an insulating material such as silicon dioxide is sometimes deposited over the outside corners of the dielectric film 26.
Second, the sidewalls 34 and 36 of the barrier layer 28 are exposed to oxidation during deposition of the dielectric film 26. Accordingly, the high temperatures encountered during the dielectric deposition process will cause the sidewalls of the barrier layer 28 to oxidize. Such an oxide increases the contact resistance of the barrier layer 28. Further, with an oxide formed on the sidewalls 34 and 36 of the barrier layer 28, the lower electrode 22 will not adhere as well to the barrier layer 28 which results in the lower electrode 22 separating from the barrier layer 28.
Third, if the barrier layer 28 does not completely overlap the polysilicon plug 20, then the surface of the polysilicon plug will oxidize during the deposition of the dielectric material 26. A critical alignment of the barrier layer 28 and the polysilicon plug 20 is required.
A solution to these problems is provided by U.S. Pat. No. 5,335,138 to Sandhu et al. This patent teaches the use of spacers positioned at each end of the lower electrode-barrier layer stack to prevent oxidation of the sidewalls of the barrier layer during deposition of the dielectric film. These spacers also provide a smooth topography for the depositon of the dielectric film. This provides the completed capacitor with a smooth topography which prevents the current leakage which occurs through sharp corners of the dielectric layer. Finally, the spacers provide a larger area for protection of the polysilicon plug from oxidation. However, the process described by Sandhu et al. requires additional processing steps and time to form the spacers.
For these reasons, a need exists in the art for a capacitor which is not subject to the limitations of the prior art. Particularly, a need exists in the art for a capacitor and a method for making a capacitor which has step coverage which eliminates charge leakage. A need also exists for a capacitor and a method for making a capacitor which prevents oxidation of the sidewalls of the lower electrode and the barrier layer. Another need exists for a capacitor and a method for making a capacitor which provide for proper placement of the lower electrode and barrier layer over the polysilicon plug. Finally, a need exists in the art for a method of making such a capacitor which will quickly and efficiently address the current needs in the art.
The present invention provides a high dielectric constant capacitor and a method for manufacturing such a capacitor. The present invention provides a capacitor with minimized current leakage, a capacitor which does not experience oxidation of the barrier layer or lower electrode during processing, and a capacitor in which the polysilicon contact is not exposed to oxidation by the barrier layer.
One aspect of the present invention is directed to a method for forming a capacitor for a semiconductor device. The method comprises the steps of: forming a contact in a layer of an insulating material, the layer of insulating material being formed over a semiconductor substrate; forming a layer of a first electrode material on the layer of insulating material, the layer of the first electrode material being formed in contact with the contact; etching the layer of the first electrode material to form a first electrode having a nodular shape; forming a layer of a dielectric material on the first electrode; and forming a second electrode on the layer of the dielectric material. In this method, the step of etching the layer of the first electrode material can be performed by either a wet etch or a facet etch.
Another aspect of the present invention is directed to another method for forming a capacitor for a semiconductor device. This method comprises the steps of: forming a contact in a layer of an insulating material, the layer of insulating material being formed over a semiconductor substrate; etching the contact to form a barrier hole; forming a layer of a barrier material in the barrier hole such that the layer of barrier material contacts the contact and is substantially coplanar with the surface of the layer of insulating material; forming a layer of a first electrode material on the layer of barrier material, the layer of first electrode material being formed on the layer of insulating material; etching the layer of the first electrode material to form a first electrode having a nodular shape; forming a layer of a dielectric material on the first electrode; and forming a second electrode on the layer of the dielectric material. In this aspect of the invention, the step of etching the first electrode can be performed by either a wet etch or a facet etch.
In an alternative embodiment of the present invention, a capacitor for a semiconductor device is formed by the steps of forming a contact in a layer of an insulating material, the layer of insulating material being formed over a semiconductor substrate; etching the contact to form a barrier hole; forming a layer of a barrier material in the barrier hole such that the layer of barrier material contacts the contact and is substantially coplanar with the surface of the layer of insulating material; forming a layer of a sacrificial material on the layer of barrier material, the layer of sacrificial material being formed on the layer of insulating material; etching an opening in the layer of sacrificial material to expose the layer of barrier material; forming a first electrode in the opening on the layer of barrier material; removing the layer of sacrificial material; forming a layer of a dielectric material on the first electrode; and forming a second electrode on the layer of the dielectric material.
A further aspect of the present invention is directed to a method for forming a semiconductor device. This method comprises the steps of: providing a semiconductor substrate; forming a layer of an insulating material over the semiconductor substrate, the layer of insulating material having a surface; forming a contact via in the layer of the insulating material; depositing a contact in the contact via; planarizing the contact to make the contact substantially coplanar with the surface of the layer of insulation material; depositing a layer of a first electrode material on the surface of the layer of insulation material, the first electrode material contacting the contact; etching the layer of the first electrode material to form a first electrode having a nodular shape; forming a layer of dielectric material on the first electrode; and forming a second electrode on the layer of dielectric material. In this aspect of the invention, the step of etching the block of the first electrode material to form a first electrode having a nodular shape is performed with either a wet etch process or a facet etch process.
A still further aspect of the present invention is directed to a method for forming a semiconductor device. This method comprises the steps of: providing a semiconductor substrate; forming a layer of an insulating material over the semiconductor substrate, the layer of insulating material having a surface; forming a contact via in the layer of the insulating material; depositing a contact in the contact via; planarizing the contact to make the contact substantially coplanar with the surface of the layer of insulation material; over etching the contact to form a barrier hole; forming a layer of a barrier material in the barrier hole; polishing the layer of barrier material so that the layer of barrier material has a surface which is substantially coplanar with the surface of the layer of insulating material; depositing a layer of a first electrode material on the surface of the layer of insulation material, the first electrode material contacting the layer of barrier material; etching the layer of the first electrode material to form a first electrode having a nodular shape; forming a layer of dielectric material on the first electrode; and forming a second electrode on the layer of dielectric material. In this method, the step of etching the block of the first electrode material to form a first electrode having a nodular shape is performed by either a wet etch process or a facet etch process.
Another aspect of the present invention is directed to a process for forming a memory array. The memory array comprises a plurality of memory cells arranged in rows and columns with each of the plurality of memory cells comprising at least one field effect transistor. The method comprises the steps of: providing a semiconductor substrate; forming sources, drains and gates for each of the field effect transistors on the semiconductor substrate; forming a layer of an insulating material over the semiconductor substrate; forming at least one contact via in the layer of insulating material, each of the contact vias communicating with one of the sources or the drains of one of the field effect transistors; forming a contact in each of the contact vias, each of the contacts contacting one of the sources or the drains of one of the field effect transistors; forming a layer of a first electrode material on the layer of insulating material on each of the contacts; etching each of the layers of first electrode material to provide a series of first electrodes, each of the first electrodes having a nodular shape and contacting the contacts; forming a layer of a dielectric material on each of the first electrodes; and forming a second electrode on each of the layers of dielectric material. In this method, the step of etching each of layers of first electrode material to provide a series of first electrodes is performed by either a wet etch process or a facet etch process.
Another aspect of the present invention is directed to a method for forming a memory array. The memory array comprises a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells comprises at least one field effect transistor. The method comprises the steps of: providing a semiconductor substrate; forming sources, drains and gates for each of the field effect transistors on the semiconductor substrate; forming a layer of an insulating material over the semiconductor substrate; forming at least one contact via in the layer of insulating material, each of the contact vias communicating with one of the source or the drain of one of the field effect transistors; forming a contact in each of the contact vias, each of the contacts contacting one of the sources or the drains of one of the field effect transistors; etching each of the contacts to provide a series of barrier holes; forming a layer of a barrier material in each of the barrier holes; forming a layer of a first electrode material on the layer of insulating material on each of the layers of barrier material; etching each of the layers of the first electrode material to provide a series of first electrodes, each of the first electrodes having a nodular shape; forming a layer of a dielectric material on each of the first electrodes; and forming a second electrode on each of the layers of dielectric material. In this method, the step of etching each of the layers of first electrode material to provide a series of first electrodes is performed by means of either a wet etch process or a facet etch process.
Still another aspect of the present invention is directed to a method for fabricating a wafer. The method comprises the steps of: providing a wafer including a semiconductor substrate; forming a repeating series of sources, drains and gates for at least one field effect transistor on each of a plurality of individual die over the semiconductor substrate; forming a layer of an insulating material over the semiconductor substrate, the layer of insulating material having a surface; forming at least one contact via in the layer of insulating material on each of the individual die, the via exposing one of the sources or the drains; forming a contact in each of the contact vias on each of the individual die, the contact contacting one of the sources or the drains and the contact being substantially coplanar with the surface of the layer of insulating material; forming a layer of a first electrode material on the contact on the surface of the layer of insulating material on each of the individual die; etching each of the layers of first electrode material to form a series of first electrodes having a nodular shape on each of the individual die; forming a layer of a dielectric material on each of the first electrodes on each of the individual die; and forming a second electrode on each of the layers of dielectric material on each of the individual die. With this method, the step of etching the layer of first electrode material is performed with either a wet etch or a facet etch.
Still another aspect of the present invention is directed to a method for fabricating a wafer. The method comprises the steps of: providing a wafer including a semiconductor substrate; forming a repeating series of sources, drains and gates for at least one field effect transistor on each of a plurality of individual die on the semiconductor substrate; forming a layer of an insulating material over the semiconductor substrate, the layer of insulating material having a surface; forming at least one contact via in the layer of insulating material on each of the individual die, the contact via exposing one of the sources or the drains; forming a contact in each of the contact vias on each of the individual die, the contact contacting one of the sources or the drains and the contact being substantially coplanar with the surface of the layer of insulating material; etching each of the contacts to form a barrier hole in each of the individual die; forming a layer of a barrier material in each of the barrier holes on each of the individual die, the barrier material being flush with the surface of the layer of insulating material; forming a layer of a first electrode material on each of the layers of barrier material on the surface of the layer of insulating material on each of the individual die; etching each of the layers of first electrode material to form a series of first electrodes having a nodular shape on each of the individual die; forming a layer of a dielectric material on each of the first electrodes on each of the individual die; and forming a second electrode on each of the layers of dielectric material on each of the individual die. In this aspect of the invention, the step of etching the layer of first electrode material is performed with either a wet etch or a facet etch.
A further aspect of the present invention is directed to a capacitor for a semiconductor device. The capacitor comprises a contact which is formed in a layer of insulating material of the semiconductor device. A first electrode is formed on the layer of insulating material. The first electrode contacts the contact and has a nodular shape. A layer of a dielectric material is formed on the first electrode. Finally, a second electrode is formed on the layer of the dielectric material.
A still further aspect of the present invention is directed to a capacitor for a semiconductor device. The capacitor includes a contact which is formed in a layer of insulating material of the semiconductor device. A layer of a barrier material is also formed in the layer of insulation material. The layer of barrier material contacts the contact. A first electrode is formed on the layer of insulating material and contacts the layer of barrier material. The first electrode has a nodular shape. A layer of a dielectric material is formed on the first electrode. Finally, a second electrode is formed on the layer of the dielectric material.
An additional aspect of the present invention is directed to a semiconductor device. The semiconductor devices includes a semiconductor substrate. A layer of an insulating material is formed over the semiconductor substrate. The layer of the insulating material defines a contact via. A contact is formed in the contact via. A first electrode is formed on the layer of insulating material. The first electrode contacts the contact and has a nodular shape. A layer of a dielectric material is formed on the first electrode and a second electrode is formed on the layer of the dielectric material.
Another aspect of the present invention is directed to a semiconductor device. The device includes a semiconductor substrate. A layer of an insulating material is formed over the semiconductor substrate. The layer defines a contact via with the semiconductor substrate. A contact is formed in the contact via. A layer of a barrier material is formed in the contact via and contacts the contact. A first electrode is formed on the layer of insulating material. The first electrode contacts the layer of barrier material and has a nodular shape. A layer of a dielectric material is formed on the first electrode and a second electrode is formed on the layer of the dielectric material.
Yet another aspect of the present invention is directed to a memory cell. The memory cell includes a semiconductor substrate having at least one field effect transistor formed therein. A layer of an insulating material is formed over the field effect transistor. The layer defines a contact via with the field effect transistor. A contact is formed in the contact via and contacts the field effect transistor. A capacitor is coupled to the field effect transistor by the contact. The capacitor includes a first electrode formed on the layer of insulating material, the first electrode contacting the contact and having a nodular shape; a layer of a dielectric material formed on the first electrode; and a second electrode formed on the layer of the dielectric material.
Still another aspect of the present invention is directed to a memory cell. The memory cell includes a semiconductor substrate. A field effect transistor is formed in the semiconductor substrate. A layer of an insulating material is formed over the field effect transistor. The layer of insulating material defines a contact via with the field effect transistor. A contact is formed in the contact via such that the contact fills at least a portion of the contact via and the contact contacts the field effect transistor. A layer of a barrier material is also formed in the contact via. The layer of barrier material contacts the contact. A capacitor is coupled to the field effect transistor by the layer of the barrier material through the contact. The capacitor includes a first electrode formed on the layer of insulating material, the first electrode contacting the layer of barrier material and the first electrode having a nodular shape; a layer of a dielectric material formed on the first electrode; and a second electrode formed on the layer of the dielectric material.
A further aspect of the present invention is directed to a memory array. The memory array comprises a plurality of memory cells arranged in rows and columns. Each of the memory cells includes a semiconductor substrate. At least one field effect transistor is formed on the semiconductor substrate. A layer of an insulating material is formed over the semiconductor substrate. The layer of the insulating material defines a contact via with the field effect transistor. A contact is formed in the contact via. The contact contacts the field effect transistor. A capacitor is coupled to the field effect transistor by the contact. The capacitor includes a first electrode formed on the layer of insulating material, the first electrode contacting the contact and having a nodular shape; a layer of a dielectric material formed on the first electrode; and a second electrode formed on the layer of the dielectric material.
A still further aspect of the present invention is directed to a memory array. The memory array comprises a plurality of memory cells arranged in rows and columns. Each of the memory cells comprises a semiconductor substrate. At least one field effect transistor is formed on the semiconductor substrate. A layer of an insulating material is formed over the semiconductor substrate. The layer of the insulating material defines a contact via with the field effect transistor. A contact is formed in the contact via and the contact contacts the field effect transistor. A capacitor is coupled to the field effect transistor by the contact. The capacitor includes a first electrode formed on the layer of insulating material, the first electrode contacting the contact and having a nodular shape; a layer of a dielectric material formed on the first electrode; and a second electrode formed on the layer of the dielectric material.
Yet still another aspect of the present invention is directed to a semiconductor wafer. The wafer includes a semiconductor substrate. A repeating series of sources, drains and gates for at least one field effect transistor are formed on each of a plurality of die on the wafer. The series of sources, drains and gates are formed over the semiconductor substrate. A layer of an insulating material is formed over the semiconductor substrate. The layer of insulating material defines a series of contact vias for each of the field effect transistors. A contact is formed in each of the contact vias. Each of the contacts contacts one of the sources, drains or gates of the field effect transistor. At least one capacitor is formed on each of the plurality of individual die. Each of the capacitors is coupled to one of the field effect transistors by one of the contacts. Each of the capacitors includes a first electrode formed on the layer of insulating material, the first electrode contacting the contact and having a nodular shape; a layer of a dielectric material formed on the first electrode; and a second electrode formed on the layer of the dielectric material.
A still further aspect of the present invention is directed to a semiconductor wafer. The wafer includes a semiconductor substrate. A repeating series of sources, drains and gates for at least one field effect transistor is formed on each of a plurality of die on the wafer. The series of sources, drains and gates is formed over the semiconductor substrate. A layer of an insulating material is formed over the semiconductor substrate. The layer of insulating material defines a series of contact vias for each of the field effect transistors. A contact is formed in at least a portion of each of the contact vias. Each of the contacts contacts one of the sources, drains or gates of the field effect transistor. A layer of a barrier material is formed in each of the contact vias. The layer of barrier material contacts the contact. At least one capacitor is formed on each of the plurality of individual die. Each of the capacitors is coupled to one of the field effect transistors by one of the layers of barrier material and one of the contacts. Each of the capacitors includes a first electrode formed on the layer of insulating material, the first electrode contacting the layer of barrier material and having a nodular shape; a layer of a dielectric material formed on the first electrode; and a second electrode formed on the layer of the dielectric material.
Other objects and advantages of the invention will be apparent from the following detailed description, the accompanying drawings and the appended claims.